1. Technical Field
The present invention relates to a memory access control device for controlling access to a memory, more particularly relates to a memory access control device for controlling access to a memory from a plurality of ports and a processing system having the same.
2. Background Art
For example, like a processing system disclosed in Japanese Patent Publication (A) No. 2002-215382, there is known a device referred to as “dynamically reconfigurable hardware” able to change the configuration of a circuit during its operation.
Dynamically reconfigurable hardware is generally connected to a system bus together with a CPU, system memory, etc. and performs processing in cooperation with the CPU. In the process of the processing, when data for defining the circuit configuration, referred to as configuration information (CS), is written into a specific register of the dynamically reconfigurable hardware, the circuit is dynamically reconfigured based on the written configuration information. The dynamically reconfigurable hardware is generally provided inside it with a local memory for storing the data to be processed. When processing is performed in dynamically reconfigurable hardware, the data to be processed is transferred once from the system memory via the system bus to the local memory (LM), processed there, then written back to the system memory again and utilized at the CPU etc.
FIG. 11 is a block diagram of an example of the configuration of general dynamically reconfigurable hardware. The dynamically reconfigurable hardware has write address generators (abbreviated as AGWs) 1-0 to 1-3, read address generators (abbreviated as AGRs) 2-0 to 2-3, LMs 3-0 to 3-3, processor units (PUs) 4-0 to 4-3, and a configuration information register (CS-REG) 5.
An AGW 1-n (n indicates an integer of 0 to 3) generates the destination address when writing data of the result of processing in a PU 4-n into an LM 3-n. An AGR 2-n generates the destination address when reading the data to be stored in the TM 3-n and outputting it to the PU 4-n. The address generation operations in the AGW 1-n and the AGR 2-n are determined based on the configuration information CS supplied from the CS-REG5. The LM 3-n stores the data to be processed of the PU 4-n and the data of the result of the processing. The PU 4-n performs predetermined processing for the data stored in the LM 3-n and stores the processing result in the LM 3-n again. The PU 4-n is reconfigured based on the configuration information CS supplied from the CE-REG5 and changes the content of the processing operation as the result of the reconfiguration. The CS-REG 5 stores the configuration information CS written via the-system bus and supplies the stored configuration information CS to the AGW 1-n, AGR 2-n, and PU 4-n.
According to the dynamically reconfigurable hardware shown in FIG. 11, the content of the operation generating the addresses in the AGW 1-n and the AGR 2-n and the content of the processing operation in the PU 4-n can be dynamically changed in accordance with the configuration information CS written into the CS-REG 5 via the system bus.
When the processing is carried out in the PUs (4-0 to 4-3), the data to be processed is transferred to the LMs (3-0 to 3-3) determined for each PU via the system bus. The data transferred to the LMs (3-0 to 3-3) are read by the corresponding PUs (4-0 to 4-3) and subjected to predetermined processing in accordance with the configuration information CS. The data of the processing results are written into the corresponding LMs (3-0 to 3-3) and written back to the not shown system memory via the system bus.
In the dynamically reconfigurable hardware shown in FIG. 11, local memories (IMs), address generators (AGW, AGR), and processor units (PUs) are provided in one-to-one correspondence. For example, addresses generated in the AGW 1-0 and AGR 2-0 are limited to addresses for accessing the LM 3-0 and cannot be utilized for access to the other LMs. In the same way, the destination of the data read out from the LM 3-0 is limited to the PU 4-0, and the destination of the processing result output from the PU 4-0 is limited to the TM 3-0. In this way, in dynamically reconfigurable hardware provided with a plurality of PUs and a plurality of LMs, there are restrictions in the access of the PUs with respect to the IMs, therefore there are the various disadvantages mentioned below.
For example, processing operations involving transfer of data among PUs, for example, the use of processing result of the PU 4-0 in the PU 4-1, cannot be executed inside the dynamically reconfigurable hardware.
Since assignment of storage regions with respect to PUs is limited, for example, when the processing operations are stopped in part of the PUs, the LMs corresponding to the stopped PUs are not utilized at all and become wasted.
In the dynamically reconfigurable hardware shown in FIG. 11, while a PU is accessing an LM, processing for writing the data to be processed of the dynamically reconfigurable hardware from the system bus to the LM and processing for reading the processing result from the LM and outputting the same to the system bus cannot be executed.
Accordingly, in order to access the LM from the system bus, as shown in FIG. 12, it is necessary to switch (change) the supplying side of the address to the LM from the internal address generator to the external address bus BA#ex in the state where the PU is stopped and, at the same time, switch an input/output port of the LM from the internal PU to the external data bus BD#ex.
In this way, the PU must be stopped in order to access the LM inside the dynamically reconfigurable hardware from an external bus, therefore there is the disadvantage of occurrence of delay due to the stopping of the processing.
Therefore, for example as shown in FIG. 13, the method of overcoming the above disadvantage by replacing the above plurality of independent LMs by single multi-port memory can be considered. By using a multi-port memory, it becomes possible to simultaneously access the address space of the entire memory from a plurality of input/output ports, therefore a processing operation involving the transfer of data among PUs becomes possible and, at the same time, the degree of freedom of the assignment of storage regions with respect to the PUs can be raised. However, in general, when realizing a multi-port memory as a semiconductor integrated circuit, the area becomes very large, therefore, when using this, the disadvantage is encountered of inviting soaring costs.